1. Field of the Invention
The present invention generally relates to field shield in shallow trench isolation and independent isolation biasing of actively isolated devices on a semiconductor chip.
2. Description of the Related Art
Conventional electronic and computer systems utilize silicon wafers with a complex arrangement of devices such as capacitors, resistors and transistors for microprocessing. The devices are located on the surface of the silicon wafer, which is itself a conductor. Thus, it is necessary to isolate areas of the wafer to prevent undesired parasitic currents among neighboring devices.
The isolation is typically accomplished using a technique called shallow trench isolation (STI). STI involves identifying an area of the substrate 10 (e.g., silicon) in which no current is desired. Then, a hole or shallow trench 13 is created, as shown in FIG. 1a. Next, as shown in FIG. 1b, the trench is filled with an STI liner 1 and an insulator STI fill (e.g. oxide) 2. The surface of the substrate 10 is planarized as shown in FIG. 1c. Devices (e.g., transistors) 15 are formed on the substrate 10. As shown in FIG. 1d, each device 15 has a device gate 3, a device gate sidewall dielectric 4, and a device source/drain diffusion 5.
STI isolates adjacent devices but it does not permit the electrical behavior independent tailoring of current-voltage characteristics of individual devices.
STI, as practiced by the present art, does not provide electrical control elements within isolation regions which may be used for selective tailoring of the electrical behavior of individual MOSFETs. To provide optimal performance in typical CMOS applications unique values of threshold voltage (Vt) are desirable for specific devices. For example, in DRAM applications relatively low threshold voltages (e.g., 0.4 V) are desired for certain high-performance MOSFETs (e.g., sense amplifiers, wordline drivers) which support (are connected to) the actual memory array. However, in the memory array itself MOSFETs with relatively high threshold voltages are needed to avoid excessively large sub-Vt leakage. Large sub-Vt leakage current degrades data retention time of the storage capacitors in the array.
Additionally, due to manufacturing tolerances threshold voltages may vary across each chip or across a wafer. This variation may be somewhat predictable because of known spatial variation patterns of processing tools (i.e. implantation, etching, deposition). It is desirable to minimize this spatial variation in threshold voltage.
As a result of this need to selectively tailor individual threshold voltages, techniques such as selective ion implantation of dopant impurities and/or selective gate oxide thicknesses are employed. These conventional means of tailoring threshold voltages are costly, since they require additional masks and/or processing complexity.
Therefore, there is a need for providing a type of isolation among neighboring MOSFETs which may be used to selectively tailor the threshold voltage of adjacent MOSFETs by use of an imbedded electrical control element.
Another problem that exists in STI is gap fill. Normally, an oxide is placed in the STI region, but gaps which are problematic to the semiconductor function may occur in the oxide.
Therefore, there is a need for an improved isolation that permits independent control of the active devices on the silicon wafer and reduces the gap fill problem.
It is, therefore, an object of the present invention to provide a structure and method for a semiconductor device which includes a substrate comprising trenches, a plurality of devices on the substrate isolated by the trenches, conductive sidewall spacers within the trenches, and an insulator filling the trenches between the conductive sidewall spacers.
The invention also includes a contact above a surface of the substrate that is electrically connected to one of the conductive sidewall spacers and a voltage source electrically connected to the contact. The source can independently bias a one of the plurality of devices. The source can also bias a subset of the plurality of devices.
Also, the invention can include a first contact electrically connected to a first sidewall spacer and a second contact electrically connected to a second sidewall spacer. One of the plurality of devices may be independently biased by applying different voltages to the first conductive sidewall spacer and second conductive sidewall spacer.
Also, an insulator separates the conductive sidewall spacers. The first conductor and the second conductor can be field shields and can be beneath a top surface of the substrate.
A first contact may be equidistant between the first conductor and the second conductor.
The invention also comprises a method of making a semiconductor device which includes forming a plurality of trenches in a substrate, forming a plurality of devices on a substrate, forming an insulating layer on the surface of the trenches, filling the trenches with a conductor, and etching the conductor from the trench to form conductive side wall spacers. Each of the sidewall spacers is individually capacitively coupled to an adjacent device.